Manycore architectures are expected to dominate future general-purpose and application-specific computing systems. The everincreasing\r\nnumber of on-chip processor cores and the associated interconnect complexities present significant challenges in\r\nthe design, optimization and operation of these systems. In this paper we investigate the applicability of intelligent, dynamic\r\nsystem-level optimization techniques in addressing some manycore design challenges such as dynamic resource allocation. In\r\nparticular, we introduce hardware enabled system-level bidding-based algorithms as an efficient and real-time on-chip mechanism\r\nfor resource allocation in homogeneous and heterogeneous (MPSoC) manycore architectures. We have also developed a lowlevel\r\nsimulation framework, to evaluate the proposed bidding-based algorithms in several on-chip network-connected manycore\r\nconfigurations. Experimental results indicate performance improvements between 8%ââ?¬â??44%, when compared to a standard onchip\r\nstatic allocation, while achieving a balanced workload distribution. The proposed hardware was synthesized to show that it\r\nimposes a very small hardware overhead to the overall system. Power consumption of the embedded mechanism as well as energy\r\nconsumption due to additional network traffic for collecting system feedback are also estimated to be very small. The obtained\r\nresults encourage further investigation of the applicability of such intelligent, dynamic system-level algorithms for addressing\r\nadditional issues in manycore architectures.
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